High Frequency Behavioral Modeling of Second-Order Sigma Delta Modulators

Sigma delta modulators (ΣΔMs) form part of the core of today’s mixed-signal designs. They are cornerstone components of oversampled data converters. Such data converters take advantage of digital signal processing techniques and VLSI technology to provide high performance with low sensitivity to analog component imperfections and noisy conditions. The ongoing research on these devices shows the potential of ΣΔ data converters as a promising candidate for high-speed, high-resolution, and low-power mixed-signal interfaces. As for any electronic system, efficient modeling and simulation tools are essential in the design cycle of oversampled converters, particularly for their embedded ΣΔMs. Although transistor-level simulation is the most accurate approach known for these components, this method becomes impractical for complex systems due to the long computational time required. This situation has led circuit designers to consider alternate modeling techniques. Among these, the simulation of ΣΔMs using behavioral models has become the focus of attention for a large portion of the design community. This thesis presents an accurate behavioral model of a high speed, second-order, multi-bit ΣΔM using VHDL-AMS as the modeling language. The model addresses several nonidealities such as the integrator dynamics, thermal noise, jitter noise, and capacitance mismatch. The proposed model provides a reliable tool for the design of low-power, high-speed ΣΔMs. Results from simulations of a second-order multi-bit ΣΔM demonstrate the model to be valid and accurate when compared to SPICE and experimental data.